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1/18 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. high reliability seri es serial eeproms wl-csp eeprom family i 2 c bus BU9847GUL-W description BU9847GUL-W series is a serial eeprom of i 2 c bus interface method. 1.7v single power source action and actions available at 400khz. features 1) completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data(sda) 2) other devices than eeprom can be connected to the same port, saving microcontroller port. 3) actions available at 400khz clock (1.7v 5.5v) 4) 1.7 5.5v single power source action most suitable for battery use. 5) page write mode useful for initial value write at factory shipment. 6) auto erase and auto end function at data rewrite. 7) low current consumption at write action (5v) : 1.2ma (typ.) at read action (5v) : 0.2ma (typ.) at standby action (5v) : 0.1 a (typ.) 8) write mistake prevention function write (write protect) function added. write mistake prevention function at low voltage. 9) data rewrite up to 1,000,000times. 10) data kept for 40 years. 11) noise filter built in scl / sda terminal 12) shipment data all address ffh. BU9847GUL-W capacity bit format type power source voltage vcsp50l1 4kbit 5128 BU9847GUL-W 1.7~5.5v absolute maximum ratings (ta=25c) parameter symbol ratings unit impressed voltage vcc -0.3~+6.5 v permissible dissipation pd 220 *1 mw storage temperature range tstg -65~125 operating temperature range topr -40~85 terminal voltage - -0.3~vcc+1.0 v * when using at ta=25 or higher, 2.2mw (*1) to be reduced per 1 recommended action conditions parameter symbol ratings unit power source voltage vcc 1.7~5.5 v input voltage vin 0~vcc memory cell characteristics (ta=25c, vcc=1.7~5.5v) parameter limits unit min typ. max number of data rewrite times *1 1,000,000 - - times data hold years 40 - - years *1 not 100% tested no.10001eat14 page write number of pages 16byte product number BU9847GUL-W
technical note 2/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. electrical characteristics (unless otherwise specified, ta=-40~+85c, vcc=1.7~5.5v) parameter symbol limits unit conditions min. typ. max. ?high? input voltage1 v ih1 0.7vcc - vcc+1.0 v 2.5v vcc 5.5v ?low? input voltage1 v il1 -0.3 - 0.3vcc v 2.5v vcc 5.5v ?high? input voltage2 v ih2 0.8vcc - vcc+1.0 v 1.8v vcc<2.5v ?low? input voltage2 v il2 -0.3 - 0.2vcc v 1.8v vcc<2.5v ?high? input voltage3 v ih3 0.9vcc - vcc+1.0 v 1.7v vcc<1.8v ?low? input voltage3 v il3 -0.3 - 0.1vcc v 1.7v vcc<1.8v ?low? output voltage1 v ol1 - - 0.4 v i ol =3.0ma, 2.5v vcc 5.5v, (sda) ?low output voltage2 v ol2 - - 0.2 v i ol =0.7ma, 1.7v vcc<2.5v, (sda) input leak current i li -1 - 1 av in =0v~vcc output leak current i lo -1 - 1 av out =0v~vcc(sda) current consumption at action i cc1 - - 2.0 ma vcc=5.5v, f scl =400khz, t wr =5ms, byte write, page write i cc2 - - 0.5 ma vcc=5.5v, f scl =400khz random read, vurrent read, sequential read standby current i sb - - 2.0 a vcc=5.5v, sdascl=vcc, a2=gnd, wp=gnd radiation resistance design is not made. action timing characteristics (unless otherwise specified, ta=-40 +85c vcc=1.7 5.5v) parameter symbol fast-mode 1.7v vcc 5.5v unit min. typ. max. scl frequency fscl - - 400 khz data clock ?high? time thigh 0.6 - - s data clock ?low? time tlow 1.2 - - s sda, scl rise time *1 tr *1 - - 0.3 s sda< scl fall time *1 tf *1 - - 0.3 s start condition hold time thd:sta 0.6 - - s start condition setup time tsu:sta 0.6 - - s input data hold time thd:dat 0 - - ns input data setup time tsu:dat 100 - - ns output data delay time tpd 0.1 - 0.9 s output data hold time tdh 0.1 - - s stop condition setup time tsu:sto 0.6 - - s bus release time before transfer start tbuf 1.2 - - s internal write cycle time twr - - 5 ms noise removal valid period (sda, scl terminal) ti - - 0.1 s wp hold time thd:wp 0 - - ns wp setup time tsu:wp 0.1 - - s wp valid time thigh:wp 1.0 - - s *1 not 100% tested.
technical note 3/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. sync data input / output timing sda tsu:sta tsu:sto thd:sta start bit stop bit scl input read at the rise edge of scl data output in sync with the fall of scl fig.-1(a) sync data input / output timing fig.1-(b) start ? stop bit timing fig.1-(d) wp timing at write execution fig.1-(e) wp timing at write cancel at write execution, in the area from the do taken clock rise of the first data (1), to twr, set wp=?low? by setting wp ?high? in the area, write can be cancelled. when it is set wp=?high? during twr, write is forcibly ended, and data o f address under access is not guaranteed, therefore write it once again. thigh:wp wp sda d1 d0 ack ack data(1) data(n) twr scl fig.1-(c) write cycle timing sda (input) scl sda (output) t hd :sta t hd :dat t su :dat t buf t pd t dh t low t high t r t f sda d0 ack t wr scl write data -th address stop condition start condition scl sda wp hd wp ???? wr d1 d0 a ck a ck data(1) data(n) tsu wp stop condition
technical note 4/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. block diagram pin assignment and description land no. terminal name input/ output function b3 a2 input slave address setting terminal b2 gnd - reference voltage of al input / output, 0v b1 sda input/output slave and word addre ss, serial data input serial data output. a3 vcc - connect the power source. a2 wp input write protect terminal a1 scl input serial clock input characteristic data (the following values are typ. ones.) fig.2 block diagram sda scl wp a2 4kbit eeprom array address decoder slave ? word address register data register control circuit high voltage generating circuti power source voltage detection 9bit 9bit 8bit ack s tart stop vcc gnd 3 b a 1 2 a1 a2 b1 b2 a3 b3 index post fig.3 BU9847GUL-W(bottom view) 0 1 2 3 4 5 6 0123456 vcc[v] vil1,2,3[v] spec 0 1 2 3 4 5 6 0123456 vcc[v] vih1,2,3[v] spec 0 0.2 0.4 0.6 0.8 1 0123456 iol2[ma] vol2[v] spec fig.4 h input voltage vih1,2,3 (a2,scl,sda,wp) fig.5 l input voltage vil1,2,3 (a2,scl,sda,wp) fig.6 l output voltage vol2-iol2 (vcc=1.7v) ta=85c ta=25c ta=-40 ta=85c ta=25c ta=-40 ta=85c ta=25c ta=-40
technical note 5/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. 0 0.2 0.4 0.6 0.8 1 0123456 iol1[ma] vol1[v] 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] ili[a] 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] ilo[a] 0 0.5 1 1.5 2 2.5 0123456 vcc[v] icc1[ma] fscl=400khz data=aah 0 0.5 1 1.5 2 2.5 0123456 vcc[v] isb[a] 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] icc2[ma] fscl=400khz data=aah 1 10 100 1000 10000 0123456 vcc[v] fscl[khz] 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] thigh [s] 0 0.4 0.8 1.2 1.6 0123456 vcc[v] tlow[s] 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] thd:sta[s] -200 -150 -100 -50 0 50 0123456 vcc[v] thd:dat(high)[ns] -0.2 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] thd:dat(high)[ns] -200 -100 0 100 200 0123456 vcc[v] tsu:dat(high)[ns] 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] tpd0 [s] 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] tpd1 [s] fig.7 l input voltage vol1-iol1 (vcc=2.5v) fig.8 input leak current ili(a2,scl, wp) fig.9 output leak current ilo (sda) fig.10 consumption current at write action icc1 (fscl=400khz) fig.12 standby current i sb fig.11 consumption current at write action icc2 (fscl=400khz) fig.15 data clock ?l? time tlow fig.14 data clock ?h? time thigh fig.13 scl frequency f scl fig.18 input data hold time thd:dat fig.17 start condition setup time tsu:sta fig.16 start condition hold time thd:sta fig.21 output data delay time tpd1 fig.20 output data delay time tpd0 fig.19 input data setup time tsu:dat spec ta=25c ta=85c ta=-40 ta=85c spec ta=-40 ta=25c ta=85c ta=-40 ta=25c spec spec ta=85c ta=25c ta=-40 spec ta=85c ta=25c ta=-40 ta=85c ta=-40 ta=25c spec spec ta=85c ta=-40 ta=25c spec ta=85c ta=25c ta=-40 spec ta=85c ta=25c ta=-40 spec ta=85c ta=25c ta=-40c spec ta=85c ta=25c t a= 40 c spec ta=25c ta=85c ta=-40 ta=-40c ta=25c spec ta=85c ta=85c ta=25c ta=-40 spec spec ta=-40 ta=85c ta=25c spec spec
technical note 6/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(sda h) [s] 0 0.2 0.4 0.6 0.8 1 0123456 vcc[v] tdh0[s] 0 1 2 3 4 5 6 0123456 vcc[v] twr[ms] 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(scl h) [s] -0.6 -0.4 -0.2 0 0.2 0123456 vcc[v] tsu:wp[s] 0 1 2 3 4 0123456 vcc[v] tdh1[s] 0 1 2 3 4 5 0123456 vcc[v] tbuf[s] 0 1 2 3 4 5 0123456 vcc[v] tsu:sto[s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(scl l) [s] 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 vcc[v] ti(sda l) [s] 0 0.2 0.4 0.6 0.8 1 1.2 0123456 vcc[v] thigh:wp[s] fig.24 stop condition setup time tsu:sto fig.23 output data hold time tdh1 fig.22 output data hold time tdh1 fig.27 noise removal time ti (scl h) fig.26 internal write cycle time twr fig.25 bus release time before transfer start tbuf fig.28 noise removal time ti (scl l) fig.29 noise removal time ti (sda h) fig.30 noise removal time ti (sda l) fig.31 wp setup time tsu:wp fig.32 wp valid time thigh: wp ta=85c ta=25c ta=-40c spec ta=85c ta=25c ta=-40c spec spec ta=85c ta=25c ta=-40c spec ta=-40 c ta=25c t8 c spec ta=85c ta=-40 ta=25c ta=85c spec ta=-40 ta=25c spec ta=85c ta=-40 ta=25c spec ta=-40 ta=25c ta=85c spec ta=-40 ta=25c ta=85c spec ta=85c ta=-40 ta=25c spec ta=-40c ta=25c ta=85c
technical note 7/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices c onnected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communication start and end, and ?slave? that is controlled by addresses peculiar to devices. eeprom becomes ?slave?. and the device that outputs data to bys during data communication is ca lled ?transmitter?, and the device that receives data is called ?receiver ?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from ?high? down to ?low? when scl is ?high? is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) of not, theref ore, unless this condition is satisfied, any command is executed. stop condition (stop bit recognition) ? each command can be ended by sda rising from ?low? to ?high? when stop condition (stop bit), namely, scl is ?high?. acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write comm and, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? this device (this ic at slave address in put of write command , read command , and -com at data output of read command) at the receiver (receiving) side sets sda ?l ow? during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) ?low?. ? each write action outputs acknowledge signal (ack signal) ?low?, at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) ?low?. ? when acknowledge signal (ack signal) is detected, and stop condition is not s ent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack signa l) is not detected, this ic stops data transfer, and recognizes stop condition (stop bit), and ends read action. and this ic gets in standby status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to ?1010?. ? next slave addressed (a2 --- device address) are for sele cting devices, and plural ones can be used on a same bus according to the number of device addresses. ? the most insignificant bit ( w/r --- write/read ) of slave address is used for designating write or read action, and is as shown below. setting w/r to 0 --- write (setting 0 to word address setting of random read) setting w/r to 1 --- read type slave address maximum numbe r of connected buses BU9847GUL-W 1 0 1 0 a2 0 ps w/r 2 ps is page select bits. 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7 fig.33 data transfer timing sda gnd a2 scl wp vcc 1 2 3 b a
technical note 8/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. fig.34 byte write cycle ? data is written to the address designated by word address (n-th address). ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk. up to 16 bytes. and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to ?internal address increment? of ?notes on page write cycle? in p8/16.) ? as for page write cycle of BU9847GUL-W, after page select bi t (ps) of slave address is designated arbitrarily, by continuing data input of 2 bytes or mo re, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. 0 a2 w a 7 d7 1 1 0 0 w r i t e s t a r t r / w a c k s t o p word address dat a wp sd a line slave address p w a 0 d0 a c k a c k w r i t e s t a r t r / w a c k s t o p word address(n) data ( n ) wp s d a line a c k a c k data ( n+15 ) a c k slave address 10 0 1 p 0 a2 w a 7 d0 d7 d0 wa 0 fig.35 page write cycle 1 0 0 1 ps 0 a2 fig.36 difference of slave address of each type note)
technical note 9/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. notes on write cycle continuous input notes on page write cycle list of numbers of page write number of pages 16byte product number BU9847GUL-W the above numbers are maximum bytes for respective types. any types below these can be written. write protect terminal (wp) ? write protect function when wp terminal is set vcc (h level), data rewrite of all addr esses is prohibited. when it is set gnd (l level), data rewrite of all addresses is enabled. be sure to connect this termi nal to vcc or gnd, or control it to h level or l level. do not use it open. at extremely low voltage at power on/off, by setting the wp terminal ?h?, mistake write can be prevented. during twr, set the wp terminal always to ?l?. if it is set ?h ?, write is forcibly terminated. w r i t e s t a r t r / w a c k s t o p word address(n) data(n ) sda line a c k data(n+15 ) a c k slave address 10 0 1ps 0 a2 wa 7 d0 d7 d0 a c k wa 0 1 1 00 next command twr (maximum : 5ms) co m man d is no t acce pt ed fo r th is p er iod . a t stop (sto p bit), w rit e starts . s t a r t 1 0 0 1ps 0 a2 fig.38 difference of each type of slave address fig.37 page write cycle note) internal address increment page write mode wa7 ----- wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 0 0 ----- 0 1 1 1 0 0 ----- 0 1 1 1 1 0 ----- 0 0 0 0 0 --------- --------- significant bit is fixed. no digit up increment 0eh for example, when it is started from address 0eh, therefore, increment is made as below, 0eh 0fh 00h 01h ---, which please note. *0eh --- 0e in hexadecimal, therefore, 00001110 becomes a binary number. 1page = 16 bytes, but the page write cycle write time is 5ms at maximum for 16byte bulk write. it does not stand 5ms at maximum x 16 bytes = 80ms (max.).
technical note 10/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal addr ess register without designating address, and is used when to verify just after write cycle. in both the read cycles, s equential read cycle is available, and the next address data next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output. ? when ack signal ?low? after d0 is detected, and st op condition is not sent from the master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where ?h? is input to ack signal after d0 and sda signal is started at scl signal ?h?. ? when ?h? is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input ?h? to ack signal after d0, and to start sda at scl signal ?h?. ? sequential read is ended by stop condition where ?h? is input to ack signal after arbitrary d0 and sda is started at scl signal ?h?. it is necessary to input ?h? to the last ack. it is necessary to input ?h? to the last ack. w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data ( n ) a c k slave address 10 0 1 p 0 a2 wa 7 0 d0 slave address 10 0 10 a2 s t a r t d7 r / w r e a d wa 0 0 a2 d7 1 1 0 0 r e a d s t a r t r / w s t o p data sda line sla ve address ps d0 a c k a c k r e a d s t a r t r / w a c k s t o p data ( n ) sda line a c k a c k da ta ( n+x ) a c k slave address 10 0 1 ps 0 a2 d0 d7 d0 d7 fig.39 random read cycle fig.40 current read cycle fig.41 sequential read cycle 1 0 0 1 ps 0 a2 fig.42 difference of slave address of each type note)
technical note 11/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. software reset software reset is executed when to avoid malfunction after po wer on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figur e below. (refer to fig.43(a), fig.43(b) and fig.43(c).) in dummy clock input area, release the sda bus (?h? by pull up) . in dummy clock area, ack output and read data ?0? (both ?l? level) may be output from eeprom , therefore, if ?h? is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignored , therefore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ack signal sends back ?l?, then it means end of write action, while if it sends back ?h?, it means now in writing. by use of acknowledge polling, next command can be executed without waiting for twr=5ms. when to write continuously, w/r = 0, when to carry out current read cycle after write, slave address w/r = 1 is sent, and if ack signal sends back ?l?, then execute word address input and data output and so forth. 1 2 13 14 scl dummy clock x14 start x2 fig.43-(a) the case of dummy clock + start + start + command input 2 1 8 9 dummy clock x9 start fig.43-(b) the case of start + 9 dummy clocks + start + command input start normal command normal command normal command normal command sda scl sda start x 9 1 2 3 8 9 7 fig.43-(c) start x 9 + command input normal command normal command scl sda * start normal command from start input. fig.44 case to continuously write by acknowledge polling slave address word address ? s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack = low is sent back, so input next word address and data in succession. twr twr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l
technical note 12/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. wp valid timing (write cancel) wp is usually to ?h? or ?l?, but when wp is used to cancel wr ite cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp = ?h?, write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the firs t start condition of command to the rise of clock to taken in d0 of data (in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don?t care. set the setup time to rise of d0 taken scl 100ns or more. the area from the rise of scl to take in d0 to the end of internal automatic write (twr) is cancel valid area. and, when it is set wp = ?h? during twr, write is ended forcibly, data of address under access is not guaranteed, therefor e, write it once again. (refer to fig.45.) after execution of forced end by wp, standby status gets in, so there is no need to wait for twr (5ms at maximum). command cancel by start condition and stop condition during command input, by continuously inputting start condi tion and stop condition, command can be cancelled. (refer to fig.46) however, in ack output area and during data read, sda bus ma y output ?l?, and in this case, start condition and stop condition cannot be input, so reset is not available. therefor e, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. fig. 45 wp valid timing rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 rise of sda sda wp wp cancel invalid area wp cancel valid area write forced end data is not written data not guaranteed slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address fig. 46 case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition
technical note 13/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. (1) sda rise time to be determined by the capacity (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2) the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of ?h? to sda bus and r pu should sufficiently secure the input ?h? level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. v cc -i l r pu -0.2 v cc v ih r pu 0.8v cc -v ih i l ex.) when v cc =3v, i l =10 a, v ih =0.7 vcc from (2) 300 k ? r pu 0.83-0.73 1010 -6 minimum value of r pu the minimum value of r pu is determined by the following factors. (1) when ic outputs low, it should be satisf ied that volmax = 0. 4v and iolmax = 3ma. (2) volmax = 0.4v should secure the input ?l? level (vil) of microcontroller and eeprom including recommended noise margin 0.1v cc . v olmax v il ? 0.1v cc ex.) when v cc = 3v, v ol = 0.4v, i ol = 3ma, microcontroller, eeprom v il = 0.3v cc from (1), and pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the ca se there is timing where scl becomes ?hi-z?, add a pull up resistance. as for the pull up resistance, one of several k ? ~ several ten k ? is recommended in consideration of drive performance of output port of microcontroller. a2, wp process process of device address terminals (a2) check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. connect this terminal to pull up of pull down, or v cc or gnd. process of wp terminal wp terminal is the terminal that prohibits and permits write in hardware manner. in ?h? status, only read is available and write of all addresses is prohibited. in the case of ?l?, bot h are available. in the case to use it as an rom, it is recommended to connect it to pull up or v cc . in the case to use both read and write, control wp terminal or connect it to pull down or gnd. microcontroller r pu a sda terminal il il bus line capacity cbus fig.47 i/o circuit diagram i ol v cc -v ol r pu r pu v cc -v ol i ol r pu 3-0.4 3 x 10 - 3 867[ ? ] v ol = 0.4[v] v il = 0.3 x 3 =0.9 [v] therefore, the condition (2) is satisfied. BU9847GUL-W
technical note 14/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain input / output. however, when to use coms input / output of tri state to sda port, insert a series resistance rs between the pull up resistance r pu and the sda terminal of eeprom. this controls over protection of sda terminal agains t surge. therefore, even when sda port is open drain input / output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. (1) sda rise time to be determined by the capacity (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2) the bus electric potential a to be determined by rpu a nd rs at the moment when eeprom outputs ?l? to sda bus should sufficiently secure the input ?l? level (v il ) of microcontroller including recommended noise margin 0.1v cc . minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. r pu microcontroller r s eeprom fig.48 i/o circuit diagram fig.49 input / output collision timing a ck ?l? output of eeprom ?h? output of microcontroller over current flows to sda line by ?h? output of microcontroller and ?l? output of eeprom. scl sda v il -v ol -0.1v cc 1.1v cc -v il 1.13-0.33 0.33-0.4-0.13 example) when v cc =3v, v il =0.3v cc , v ol =0.4v, r pu =20k ? r s 1.67 k ? r pu +r s from (2) (v cc -v ol )r s +v ol +0.1v cc v il r s r pu 2010 3 r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il fig.50 i/o circuit diagram v cc r s v cc i 300 ?? r s 3 1010 -3 example) when vcc =3v, i = 10ma, i r s microcontroller eeprom "l" output r s r pu "h" output over current i fig.51 i/o circuit diagram
technical note 15/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. i 2 c bus input / output circuit input (a2,scl) input / output (sda) input (wp) fig.52 input pin circuit diagram fig.53 input / output pin circuit diagram fig.54 input pin circuit diagram
technical note 16/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. notes on power on at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent th is, function of por circuit and lvcc circui t are equipped. to assure the action, observe the following conditions at power on. 1. set sda= ?h? and scl = ?l? or ?h?. 2. start power source so as to satisfy the recommended conditions of tr, toff, and vbot for operating por circuit. 3. set sda and scl so as not to become ?hi-z?. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes ?l? at power on. control scl and sda as shown below, to make scl and, ?h? and ?h?. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset (p10). c) in the case when the above conditions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and prev ents wrong write. at lvcc voltage (typ. = 1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malf unction may occur, therefore, for removing tese, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment , attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. recommended conditons of tr, toff, vbot tr toff vbot 10ms or below 10ms or higher 0.3v or below 100ms or below 10ms or higher 0.2v or below toff tr vbot 0 v cc tlow tsu:dat tdh a fter vcc becomes stable scl v cc sda tsu:dat a fter vcc becomes stable fig. 55 rise waveform diagram fig.56 when scl =?h? and sda = ?l? fig.57 when scl = ?h? and sda = ?l?
technical note 17/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. cautions on use (1) described numeric values and data are design repr esentative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluct uations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperature exceeding the absolute ma ximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that eac h terminal voltage is lower than that of gnd terminal. (5) thermal design in considereation of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay su fficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause ma lfunction, therefore, ev aluate design sufficiently.
technical note 18/18 BU9847GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. ordering part number b u 9 8 4 7 g u l - w e 2 part no. part no. package gul : vcsp50l1 w-cell packaging and forming specification e2: embossed tape and reel (unit : mm) vcsp50l1 (BU9847GUL-W) s 0.08 s a ba 0.05 1pin mark 3 0.4750.05 6- 0.250.05 1.950.05 2 ( 0.15)index post 1 0.28 0.05 b 0.55max 1.060.05 a 0.100.05 0.5 p=0.52 b ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () direction of feed reel 1pin
r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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